7477 datasheet(98/361 Pages) RENESAS

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HARDWARE

1-91

7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

2 Communication format

The half-duplex data communication or the full-duplex data communication are available.

2 Synchronous clock

The internal clock or the external clock can be selected as a synchronous clock by bit 2 of the Serial

I/O mode register (SM: address 00DC16).

q The synchronous clock for the case where the internal clock is selected is shown below.

Notes 1: In the 7470 group, f(XCIN) is not available.

2: When selecting a divided signal of f(XCIN), set the system clock to the low-speed mode

by bit 7 of the CPU mode register.

q When the external clock is selected, the synchronous clock is an external clock input from the P16/

CLK pin.

Notes on external clock selection

q When writing data into the Serial I/O register, perform a write operation while the synchronous

clock is at “H.”

q The shift operation of the Serial I/O register is continued while the synchronous clock is input to

the Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end

of 8 cycles. (When the internal clock is selected, the synchronous clock stops automatically.)

q Set the “H” and “L” widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL

[s] > 2/(system clock frequency [Hz]). For example, when the system clock is 8 MHz, use a clock

of 2 MHz or less (duty ratio 50 %).

2 Shift clock

Usually, when a clock synchronous transfer is performed between 2 microcomputers, one microcomputer

selects the internal clock and outputs the 8 shift clock pulses generated by a start of transfer

operation from the P16/CLK pin. The other microcomputer selects the external clock and uses the

clock input from the CLK pin as a synchronous clock.

2 SRDY signal, SARDY signal

A Serial I/O transfer ready status can be known to the outside by outputting the SRDY signal and the

SARDY signal.

• f(XIN)/8

• f(XIN)/16

• f(XIN)/32

• f(XIN)/512

• f(XCIN)/8

• f(XCIN)/16

• f(XCIN)/32

• f(XCIN)/512





















When the system clock is f(XIN)

When the system clock is f(XCIN)

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