7477 datasheet(102/361 Pages) RENESAS

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HARDWARE

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7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

2 Receive operation of Serial I/O

The receive operation of the Serial I/O is described below.

q Start of receive operation

Receive operation begins by writing the following data into the Serial I/O register (SIO: address

00DD16)V2 in the receive enable state.V1

• Transmit data in the full-duplex data communication

• Arbitrary dummy data in the half-duplex data communication

At the time when this data has been written, “7” is set in the Serial I/O counter (address 00DE16,

bit 4 – 6), so that the synchronous clock is forced to go to “H.”

V 1: State in which the register for receive operation has been initialized. Refer to “[Receive setting

method]” which will be described later.

V 2: When the external clock is selected, perform a write operation while the synchronous clock is

at “H.”

q Receive operation

1Receive data is input from the P14/SIN pin to the Serial I/O register in synchronization with the

rise of the synchronous clock. At this time, the Serial I/O counter is decremented by 1.

2Receive data is input starting into the most significant bit of the Serial I/O register. Each time one

bit is input, the contents of the Serial I/O register are shifted by 1 in the direction of the least

significant bit.

3After the receive shift operation is completed, an interrupt request occurs at the rise of the last

cycle of the synchronous clock, so that the Serial I/O interrupt request bit is set to “1”.V3

V3: When the internal clock is selected as a synchronous clock, the shift clock supply to the Serial

I/O register is automatically stopped after 8-bit data is transmitted (the Serial I/O counter overflows).

When the external clock is selected, the contents of the Serial I/O register are continuously

sifted while the synchronous clock is input. Accordingly, stop it externally.

q When using the SRDY output

At the time when data has been written into the Serial I/O register, the level of the SRDY signal

changes from “H” to “L” and the level of the SARDY signal changes from “L” to “H,” by which a

receive ready state can be known externally. The SRDY signal goes to “H” at the first fall of the

synchronous clock and the SARDY signal goes to “L” at the rise of the last cycle of the synchronous

clock.

Figure 1.13A.4 shows a receive operation and Figure 1.13A.5 shows a receive timing chart.

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