7477 datasheet(90/361 Pages) RENESAS

90 / 361 page

1-83

7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.12 Timers

Fig. 1.12.11 Structure of Timers 1 to 4

1.12.6 Related registers

(1) Timer 1, Timer 2, Timer 3, Timer 4 (T1 to T4: Address 00F016 to 00F316)

Each Timer is a register consisting of 8 bits.

Read

The contents (count value) of the Timer are read by reading the timer.

Write

When data is written to the Timer, this data is set in the Timer and the Timer latch at the same

time.

When data is written into the Timer being in count operation in the PWM mode, the written data

is set only in the Timer latch.

Refer to “1.12.4 Updating of contents of Timer and Timer latch.”

VTimer latch

The Timer latch is a register that holds a value to be automatically transferred (reloaded) to the

Timer as its initial value when the Timer overflows. It is impossible to read the contents of the

Timer latch.

Figure 1.12.11 shows a structure of Timer.

Note :

b7 b6 b5 b4 b3 b2 b1 b0

Timer 1, Timer 2, Timer 3, Timer 4 (T1, T2, T3, T4)

[Address 00F016, 00F116, 00F216,

Function

At reset RW

•Set “0016 to FF16.”

•The value is decremented by 1 each time a

count source is input.

•Each Timer values are set to the respective

counter.

•The count values are read out by reading the

respective timer.

(Note)

Timers 1 to 4

Timers 1 and 2 are undefined.

Timer 3 is “FF16.”

Timer 4 is “0716.”

00F316]

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