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EM6819 Datasheet(PDF) 49 Page - EM Microelectronic - MARIN SA |
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EM6819 Datasheet(HTML) 49 Page - EM Microelectronic - MARIN SA |
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49 / 154 page  R EM6819 Copyright © 2009, EM Microelectronic-Marin SA 07 /09 – rev.D 49 www.emmicroelectronic.com 9.2.3 PRESCALER1 CLOCK SELECTION The Prescaler1 input clock Ck_Pr1 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr1. SelCkPr1 Prescaler1 Clock 000 Ck_Hi (divided by 1) 001 Ck_Hi divided by 2 010 Ck_Hi divided by 4 011 Ck_Hi divided by 8 default 100 Ck_Lo (divided by 1) Others Ck_Hi divided by 8 The default Prescaler1 clock source after system reset (ResSys) shall be Ck_Hi divided by 8 (selection 0x3). ReqCkHi or ReqCkLo signals are asserted to the Hi- or Low frequency clock switches depending of the Prescaler1 multiplexer selection. 9.2.4 PRESCALER 2 CLOCK SELECTION The Prescaler2 input clock Ck_Pr2 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr2. SelCkPr2 Prescaler2 Clock 000 Ck_Hi (divided by 1) 001 Ck_Hi divided by 2 010 Ck_Hi divided by 4 011 Ck_Hi divided by 8 100 Ck_Lo (divided by 1) Others 1xx Ck_Lo (divided by 1) The default Prescaler2 clock source after system reset (res_sys) shall be Ck_Lo divided by 1 (selection 0x4). ReqCkHi or ReqCkLo signals are asserted to the Hi- or Low frequency clock switches depending of the Prescaler2 multiplexer selection. |
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