EM6819 datasheet(98/154 Pages) EMMICRO

98 / 154 page

EM6819

07 /09 – rev.D

www.emmicroelectronic.com

18.1 SCLK - SPI MASTER/ SLAVE MODE AND CLOCK SELECTION

Master and Slave mode as well as master mode clock selection are done in register RegSPICfg1 bits SPIMode. In

Slave mode the serial input clock is coming from PA6, PB2 or PC6 input. The selection depends on SPISelSClk bits in

SCLK Frequency selection

SCLK Slave mode input selection

SPIMode

SCLK base clock

Input

terminal

Input condition

SPIMode[2:0]

SLAVE Mode SCLK from port inputs

Slave Mode

000

from PA6, PB2 PC6

PA6

SPISelSClk='00'

PA6InpE='1'

000 (slave)

Master mode, Prescaler 2 clocks

PB2

SPISelSClk='01'

PB2InpE='1'

000 (slave)

001

Ck_Hi

PC6

SPISelSClk='10'

PC6InpE='1'

000 (slave)

010

Pr2Ck9

PA6

SPISelSClk='11'

PA6InpE='1'

000 (slave)

011

Pr2Ck8

SCLK Master mode output selection

100

Pr2Ck7

Output

terminal

Output condition

Master mode, Prescaler 1 clocks

Master Mode

101

Ck_Lo

PA6

PA6OutSel[1:0]='01'

PA6OE='1'

110

Pr1Ck13

PB2

PB2OutSel[1:0]='01'

PB2OE='1'

111

Pr1Ck12

PC6

PC6OutSel[1:0]='01'

PC6OE='1'

The used PA, PB and PC IO port terminals must be set up for SPI before SPIStart is set high.

Following table shows the different SCLK clock possibilities RTZ and RTO with the internal shift clock dependencies.

SPIRTO

SPINegEdg SCLK pulse

SCLK IDLE

value

ShiftEdge

Clock

type

Example on SCLK

High Pulse

High

Pos edge

RTZ

High Pulse

High

Neg edge

RTZ

Low pulse

Low

Pos edge

RTO

Low pulse

Low

Neg edge

RTO

SPIRTO defines a RTZ clock type if set to ‘1’ or RTO clock type if set to ‘0’

SPINegEdg defines the internal shift register shift clock edge, set to ‘1’ shift takes place on the negative SCLK clock

edge. Set to ‘0’, the shift will take on the positive SCLK clock edge. Both bits are placed in register RegSPICfg1.

EM6819 Datasheet(PDF) 98 Page - EM Microelectronic - MARIN SA

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