EM6819 datasheet(33/154 Pages) EMMICRO

33 / 154 page

EM6819

07 /09 – rev.D

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NVM MEMORY

4.1 INTRODUCTION

The circuits Non Volatile Memory (NVM) is used to store the application softwarebut it may also be used to store data

(constants or variables). The same physical memory area is shared between the instruction code and the data’s. The

boundary in this general purpose NMV memory (GPNVM) between the instruction code and the data’s is not fixed in

detail by hardware but given by the linker after compilation.

The data read access in NVM (see chapter “Read data in NVM”) is executed as a simple register access.

The data write access in NVM (see chapter “Write data in NVM”) is not executed with a simple MOVE. It is necessary to

store the data’s in an intermediate memory called RAM cache and to execute an API sub-routine in the ROM.

NVM data read access needs 2 CPU cycles, 1

st the read instruction followed with an NVM data access. During the date

access phase the CPU is in a wait state. The CR816 instruction is a 22 bits wide bus. When the CPU reads the NVM

through the data’s bus, 22 bits are read but only 2 bytes (16-bits) are accessed (the other 6 bits are used for

verification).

Note:

If the additional 6 bits are not equal to 0x3F, the read access to the previous read pair of bytes is denied. The system

interprets this access as a forbidden access to the program memory area (code protection feature)

Instruction read by CPU is straight foreward; all instruction read take 1 CPU cycle.

4.2 NVM ARCHITECTURE

The NVM is divided in 6 sectors, each sector is devided in 64 rows and each row contains either 16 instructions or 32

data bytes. A single row shall not share instructions and data bytes. From the CPU data bus interface point of view, the

NVM is mapped from address 0x4000 to 0x6FFF as shown in the following diagram.

Figure 3, NVM architecture

Note:

The row 63 and 62 of sector 5 is reserved for trimming word and unique ID code. Write access in this row is denied.

The row 61 of sector 5 is used for NVM memory dump and external read/write access protection.

EM6819 Datasheet(PDF) 33 Page - EM Microelectronic - MARIN SA