EM6819 datasheet(97/154 Pages) EMMICRO

97 / 154 page

EM6819

07 /09 – rev.D

www.emmicroelectronic.com

18.

SPI – SERIAL INTERFACE

The circuit contains a synchronous 3-wire (SDI, SDOUT and SCLK) master and slave serial interface. Its ports are

mapped on different PA, PB and PC IO terminals.

•

SCLK:

Serial Clock Input/ Output:

Input in Slave mode, Output in Master mode

•

SDIN:

Serial Interface Data Input.

Input in Master and Slave mode

•

SDOUT:

Serial Interface Data Output.

Output in Master and Slave mode

The serial interface always transmits or receives 8-bit packages at a time, followed by an interrupt request allowing the

CPU to treat the data.

An Interrupt IntSPIStart is generated at transmission start and an IntSPIStop at the end of the transmission.

An Event EvtSPI is generated at transmission start and at the end of the transmission.

The interface may also be used to generate a fix datastream output by using the Auto-Start mode.

The internal shift register clock edge is user selectable; the interface may run on RTZ (Return To Zero) or RTO (Return

to One) type of clocks

The full SPI setup shall be configured before enabling the SPI (SPIEn=’1’). Once enabled the configuration must not be

changes anymore.

While SPIEn is ‘0’, SPIStart is reset. SPIEn must be written ‘1’ before SPIStart is set.

The transmission may start as soon as SPIStart is set ‘1’. Always make first full SPI setup and only at the end set the

bit SPIStart to ‘1’ to begin the data exchange.

The register RegSPIDOut and RegSPIDIn act as a buffer for outgoing and incoming data. The RegSPIDOut must be

written before the transmission starts. The RegSPIDIn will be updated after the 8

th active clock with the actual received

input data.

The transmission direction is configurable with bit SPIMSB1st. Set to ‘1’ the first transmission bit is the MSB bit , if set

‘0’ then it is the LSB bit.

Figure 24, Serial Interface Architecture

EM6819 Datasheet(PDF) 97 Page - EM Microelectronic - MARIN SA