EM6819 datasheet(32/154 Pages) EMMICRO

32 / 154 page

EM6819

07 /09 – rev.D

www.emmicroelectronic.com

CPU CORE CR816

The full detail of the used CoolRISC 816L core is described in [1].

A brief overview of its highlights is given

below.

8-bits RISC register-memory

processor based on a Harvard

architecture

3 stage pipeline (no delay slots or

branch delays)

176 Kbytes max Program Memory

size (64 KInstruction, 22 bit wide)

64 Kbytes max Data Memory size

(organized in 256 x 256 Kbytes

pages)

8 max hardware subroutines and

unlimited software subroutines

8 bit x 8 bit hardware multiplier

5 addressing modes

direct addressing

indexed addressing with

immediate offset

indexed addressing with

indexed addressing with post-

incrementation of the offset

indexed addressing with pre-

decrementaion of the offset

16 CPU internal registers (Accu,

general purpose, Index, offset, status)

The Instruction Set is composed of

Branch Instructions

Transfer Instructions

Arithmetic and Logical Instructions

Special Instructions

Unlike

most

RISC

processors,

the

CR816L

provides

instructions

which

can

perform

arithmetic

and

logical

operations with operands stored either in the data memory or

in internal registers.

Similarly to classic 8-bit processors, the CR816L architecture

provides an accumulator located at the ALU output that stores

the last ALU result.

All arithmetic operations support both signed and unsigned

operations.

3.1 PM_MISS FUNCTION (FLASH READ MONITOR)

In extreme conditons (very low temperature and ck_hi > 15MHz) the NVM time access could be longer than a CPU

cycle. In this case a pm_miss is generated, meaning that the CPU will automatically wait an additional cycle before to

fetch the current instruction read in the NVM. Doing so, it guaranttees that the system never fails even if the CPU is

running faster than the NVM. Interrupt of priority 0 Int0StsPmMiss is generated on each pm_miss.

EM6819 Datasheet(PDF) 32 Page - EM Microelectronic - MARIN SA

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