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ATtiny48 Datasheet(PDF) 72 Page - ATMEL Corporation

Part # ATtiny48
Description  8-bit Microcontroller with 4/8K Bytes In-System Programmable Flash
PDF  266 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATtiny48 Datasheet(HTML) 72 Page - ATMEL Corporation

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72
8008C–AVR–03/09
ATtiny48/88
10.4
Register Description
10.4.1
MCUCR – MCU Control Register
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-
figuring the Pin” on page 56 for more details about this feature.
10.4.2
PORTCR – Port Control Register
• Bits 7..4 – BBMx: Break-Before-Make Mode Enable
When these bits are written to one, the port-wise Break-Before-Make mode is activated. The
intermediate tri-state cycle is then inserted when writing DDRxn to make an output. For further
information, see “Break-Before-Make Switching” on page 57.
• Bits 3..0 – PUDx: Port-Wise Pull-up Disable
When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled
even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn}
= 0b01). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD)
Table 10-13. Overriding Signals for Alternate Functions in PD3..PD0
Signal
Name
PD3/INT1/PCINT19
PD2/INT0/PCINT18
PD1/PCINT17
PD0/PCINT16
PUOE
0
000
PUO
0
000
DDOE
0
0
0
0
DDOV
0
0
0
0
PVOE
0
000
PVOV
0
000
DIEOE
INT1 ENABLE +
PCINT19 • PCIE2
INT0 ENABLE +
PCINT18 • PCIE1
PCINT17 • PCIE2
PCINT16 • PCIE2
DIEOV
1
111
DI
PCINT19 INPUT
INT1 INPUT
PCINT18 INPUT
INT0 INPUT
PCINT17 INPUT
PCINT16 INPUT
AIO
–
–––
Bit
7
6
5
4
3
2
1
0
–
BPDS
BPDSE
PUD
–
–
–
–
MCUCR
Read/Write
R
R/W
R/W
R/W
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BBMD
BBMC
BBMB
BBMA
PUDD
PUDC
PUDB
PUDA
PORTCR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0



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