ATtiny48 datasheet(76/266 Pages) ATMEL

76 / 266 page

8008C–AVR–03/09

ATtiny48/88

ter or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing

Timer/Counter0 counter value and so on.

The definitions in Table 11-1 are used extensively throughout the document.

11.2.2

Registers

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit

registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the

Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-

rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment its value. The Timer/Counter is inactive when no clock source is selected. The

output from the Clock Select logic is referred to as the timer clock (clk

T0).

The Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter

value at all times. The compare match event will also set the Compare Flag (OCF0A or OCF0B)

which can be used to generate an Output Compare interrupt request.

11.3

Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits

located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and pres-

caler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 112.

11.4

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

11-2 shows a block diagram of the counter and its surroundings.

Figure 11-2. Counter Unit Block Diagram

Table 11-1.

Definitions

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR0A Register. The assignment is depen-

dent on the mode of operation.

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

clear

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