ATtiny48 datasheet(77/266 Pages) ATMEL

77 / 266 page

8008C–AVR–03/09

ATtiny48/88

Signal description (internal signals):

count

Increment or decrement TCNT0 by 1.

clear

Clear TCNT0 (set all bits to zero).

clk

Timer/Counter clock, referred to as clk

T0 in the following.

top

Signalize that TCNT0 has reached maximum value.

Depending of the mode of operation used, the counter is cleared or incremented at each timer

clock (clk

T0). clkT0 can be generated from an external or internal clock source, selected by the

Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped.

However, the TCNT0 value can be accessed by the CPU, regardless of whether clk

T0 is present

or not. A CPU write overrides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the Clear Timer on Compare Match bit

(CTC0) located in the Timer/Counter Control Register (TCCR0A). For more details about

advanced counting sequences, see “Modes of Operation” on page 78.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by

the CTC0 bit. TOV0 can be used for generating a CPU interrupt.

11.5

Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers

(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a

match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit

location.

Figure 11-3 shows a block diagram of the Output Compare unit.

Figure 11-3. Output Compare Unit, Block Diagram

11.5.1

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

DATA BUS

TCNTn

ATtiny48 Datasheet(PDF) 77 Page - ATMEL Corporation

ATtiny48 Datasheet(HTML) 77 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL