ATtiny48 datasheet(45/266 Pages) ATMEL

45 / 266 page

8008C–AVR–03/09

ATtiny48/88

ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and

System Reset Mode, WDIE must be set after each interrupt. This should however not be done

within the interrupt service routine itself, as this might compromise the safety-function of the

Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-

tem Reset will be applied.

•Bit 4 – WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,

and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

•Bit 3 – WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is

set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-

ditions causing failure, and a safe start-up after the failure.

• Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler Bits 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-

ning. The different prescaling values and their corresponding time-out periods are shown in

Table 8-3 on page 45.

Table 8-2.

Watchdog Timer Configuration

WDTON

WDE

WDIE

Mode

Action on Time-out

Stopped

None

Interrupt Mode

Interrupt

System Reset Mode

Reset

Interrupt & System Reset Mode

Interrupt, then go to

System Reset Mode

Reset

Table 8-3.

Watchdog Timer Prescale Select

WDP3

WDP2

WDP1

WDP0

Number of

WDT Oscillator Cycles

Typical Time-out at

CC = 5.0V

2K (2048) cycles

16 ms

4K (4096) cycles

32 ms

8K (8192) cycles

64 ms

16K (16384) cycles

0.125 s

32K (32768) cycles

0.25 s

64K (65536) cycles

0.5 s

128K (131072) cycles

1.0 s

256K (262144) cycles

2.0 s

512K (524288) cycles

4.0 s

1024K (1048576) cycles

8.0 s

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