ATtiny48 datasheet(85/266 Pages) ATMEL

85 / 266 page

8008C–AVR–03/09

ATtiny48/88

For actual placement of I/O pins, refer to “Pinout of ATtiny48/88” on page 2. CPU accessible I/O

Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register

and bit locations are listed in the “Register Description” on page 105.

The PRTIM1 bit in “PRR – Power Reduction Register” on page 37 must be written to zero to

enable Timer/Counter1 module.

12.2.1

Registers

The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis-

ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-

bit registers. These procedures are described in the section “Accessing 16-bit Registers” on

page 86. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU

access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible

in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with the Timer

Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk

T1).

The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun-

ter value at all time. The result of the compare can be used by the Waveform Generator to

generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See “Out-

put Compare Units” on page 92.. The compare match event will also set the Compare Match

Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-

gered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See

“Analog Comparator” on page 155.) The Input Capture unit includes a digital filtering unit (Noise

Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined

by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using

OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a

PWM output. However, the TOP value will in this case be double buffered allowing the TOP

value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used

as an alternative, freeing the OCR1A to be used as PWM output.

12.2.2

Definitions

The following definitions are used extensively throughout the section:

Table 12-1.

BOTTOM

The counter reaches the BOTTOM when it becomes 0x0000.

MAX

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,

or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is

dependent of the mode of operation.

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