ATtiny48 datasheet(37/266 Pages) ATMEL

37 / 266 page

8008C–AVR–03/09

ATtiny48/88

7.4.2

MCUCR – MCU Control Register

• Bits 7, 3..0 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 6 – BODS: BOD Sleep

The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 7-2

on page 36. Writing to the BODS bit is controlled by a timed sequence and an enable bit,

BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first

be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to

zero within four clock cycles.

The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed

while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is

automatically cleared after three clock cycles.

• Bit 5 – BODSE: BOD Sleep Enable

BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable

is controlled by a timed sequence.

7.4.3

PRR – Power Reduction Register

The Power Reduction Register (PRR) provides a method to stop the clock to individual peripher-

als to reduce power consumption. The current state of the peripheral is frozen and the I/O

registers can not be read or written. Resources used by the peripheral when stopping the clock

will remain occupied, hence the peripheral should in most cases be disabled before stopping the

clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the

same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. In all other sleep modes, the clock is already stopped.

• Bit 7 – PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When

waking up the TWI again, the TWI should be re initialized to ensure proper operation.

• Bits 6, 4, 1 – Res: Reserved

These bits are reserved and will always read zero.

• Bit 5 – PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

Bit

–

BODS

BODSE

PUD

–

MCUCR

Read/Write

R/W

Initial Value

Bit

210

PRTWI

–

PRTIM0

–

PRTIM1

PRSPI

–

PRADC

PRR

Read/Write

R/W

Initial Value

ATtiny48 Datasheet(PDF) 37 Page - ATMEL Corporation

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