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ATtiny48 Datasheet(PDF) 22 Page - ATMEL Corporation |
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ATtiny48 Datasheet(HTML) 22 Page - ATMEL Corporation |
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22 / 266 page  22 8008C–AVR–03/09 ATtiny48/88 5.5 Register Description 5.5.1 EEARH and EEARL – EEPROM Address Register • Bits 15..6 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 5..0 – EEAR5..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 64/64 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63/63. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 5.5.2 EEDR – EEPROM Data Register • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 5.5.3 EECR – EEPROM Control Register • Bits 7..6 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be trig- gered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. While EEPE Bit 151413121110 9 8 – ––– –– – - EEARH - - EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 654 32 10 Read/Write RR RR RR RR R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 0 XX XX XX Bit 7 654 32 10 MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7654 3 2 10 – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 |
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