ATtiny48 datasheet(25/266 Pages) ATMEL

25 / 266 page

8008C–AVR–03/09

ATtiny48/88

System Clock and Clock Options

6.1

Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 33. The clock systems are detailed below.

Figure 6-1.

Clock Distribution

6.1.1

CPU Clock – clk

CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

6.1.2

I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules such as Timer/Counters, the Serial

Peripheral Interface and the External Interrupt module. Note, that some external interrupts are

detected by asynchronous logic, meaning they are recognized even if the I/O clock is halted.

Also note that the start condition detection of the Two-Wire Interface module is asynchronous,

meaning TWI address recognition works in all sleep modes (even when clk

I/O is halted).

6.1.3

Flash Clock – clk

FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

CLOCK CONTROL UNIT

GENERAL

I/O MODULES

CPU

CORE

WATCHDOG

TIMER

RESET

LOGIC

CLOCK

PRESCALER

RAM

CLOCK

SWITCH

CALIBRATED

OSCILLATOR

clk

TWIHS

SOURCE CLOCK

clk

ADC

clk

FLASH

WATCHDOG

CLOCK

clk

CPU

WATCHDOG

OSCILLATOR

EXTERNAL

CLOCK

FLASH AND

EEPROM

TWI

ADC

clk

I/O

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