ATtiny48 datasheet(30/266 Pages) ATMEL

30 / 266 page

8008C–AVR–03/09

ATtiny48/88

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is

required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

30 for details.

6.6

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. The clock also will be output during reset, and the normal operation of I/O

pin will be overridden when the fuse is programmed. Any clock source, including the internal

oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

6.7

System Clock Prescaler

The ATtiny48/88 has a system clock prescaler, and the system clock can be divided by setting

the “CLKPR – Clock Prescale Register” on page 31. This feature can be used to decrease the

system clock frequency and the power consumption when the requirement for processing power

is low. This can be used with all clock source options, and it will affect the clock frequency of the

CPU and all synchronous peripherals. clk

I/O, clkADC, clkCPU, and clkFLASH are divided by a factor

as shown in Table 6-9 on page 32.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system. It also ensures that no intermediate frequency is higher than

neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-

sponding to the new setting. The ripple counter that implements the prescaler runs at the

frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it

is not possible to determine the state of the prescaler – even if it were readable, and the exact

time it takes to switch from one clock division to the other cannot be exactly predicted. From the

time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new

clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-

vious clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must befollowed to

change the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin

CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Fast rising power

6 CK

14CK + 4 ms

Slowly rising power

6 CK

14CK + 64 ms

Reserved

Table 6-8.

Start-up Times for the External Clock Selection

SUT1..0

Power Conditions

Start-up Time

from Power-down

Additional Delay

from Reset (V

CC = 5.0V)

ATtiny48 Datasheet(PDF) 30 Page - ATMEL Corporation

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