ATtiny48 datasheet(48/266 Pages) ATMEL

48 / 266 page

8008C–AVR–03/09

ATtiny48/88

0x008

rjmp

TIMER1_CAPT

; Timer1 Capture Handler

0x009

rjmp

TIMER1_COMPA

; Timer1 Compare A Handler

0x00A

rjmp

TIMER1_COMPB

; Timer1 Compare B Handler

0x00B

rjmp

TIMER1_OVF

; Timer1 Overflow Handler

0x00C

rjmp

TIMER0_COMPA

; Timer0 Compare A Handler

0x00D

rjmp

TIMER0_COMPB

; Timer0 Compare B Handler

0x00E

rjmp

TIMER0_OVF

; Timer0 Overflow Handler

0x00F

rjmp

SPI_STC

; SPI Transfer Complete Handler

0x010

rjmp

ADC

; ADC Conversion Complete Handler

0x011

rjmp

EE_RDY

; EEPROM Ready Handler

0x012

rjmp

ANA_COMP

; Analog Comparator Handler

0x013

rjmp

TWI

; 2-wire Serial Interface Handler;

0x014

RESET:

ldi

r16, high(RAMEND); Main program start

0x015

out

SPH,r16

; Set Stack Pointer to top of RAM

0x016

ldi

r16, low(RAMEND)

0x017

out

SPL,r16

0x018

sei

; Enable interrupts

0x019

<inst> xxx

...

9.2

External Interrupts

The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT27..0 pins.

Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT27..0 pins

are configured as outputs. This feature provides a way of generating a software interrupt, as

follows.

• Pin Change Interrupt PCI3 triggers if a pin in PCINT27..24 is toggled while enabled

• Pin Change Interrupt PCI2 triggers if a pin in PCINT23..16 is toggled while enabled

• Pin Change Interrupt PCI1 triggers if a pin in PCINT15..8 is toggled while enabled

• Pin Change Interrupt PCI0 triggers if a pin in PCINT7..0 is toggled while enabled

The PCMSK3, PCMSK2, PCMSK1 and PCMSK0 registers control which pins contribute to the

pin change interrupts. Pin change interrupts on PCINT27..0 are detected asynchronously. This

means that these interrupts can be used for waking the part also from sleep modes other than

Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge, or a low level. This is

configured as described in “EICRA – External Interrupt Control Register A” on page 50. When

INT0 or INT1 interrupts are enabled and are configured as level triggered, the interrupts will trig-

ger as long as the corresponding pin is held low. Note that recognition of falling or rising edge

interrupts on INT0 or INT1 requires the presence of an I/O clock, described in “Clock Systems

and their Distribution” on page 25.

9.2.1

Low Level Interrupt

Low level interrupts on INT0 and INT1 are detected asynchronously. This means that the inter-

rupt sources can be used for waking the part also from sleep modes other than Idle (the I/O

clock is halted in all sleep modes except Idle mode).

ATtiny48 Datasheet(PDF) 48 Page - ATMEL Corporation

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