ATtiny48 datasheet(58/266 Pages) ATMEL

58 / 266 page

8008C–AVR–03/09

ATtiny48/88

Table 10-1 summarizes the control signals for the pin value.

Note:

1. Or port-wise PUDx bit in PORTCR register.

10.2.5

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit and the preceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduces a delay. Figure 10-4 shows a timing dia-

gram of the synchronization when reading an externally applied pin value. The maximum and

minimum propagation delays are denoted t

pd,max and tpd,min respectively.

Figure 10-4. Synchronization when Reading an Externally Applied Pin value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 10-5. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Table 10-1.

Port Pin Configurations

DDxn

PORTxn

PUD

(in MCUCR) (1)

I/O

Pull-up

Comment

Input

Tri-state (Hi-Z)

Input

Yes

Pxn will source current if ext. pulled low.

Input

Tri-state (Hi-Z)

Output

Output Low (Sink)

Output

Output High (Source)

XXX

in r17, PINx

0x00

0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

t pd, min

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