ATtiny48 datasheet(84/266 Pages) ATMEL

84 / 266 page

8008C–AVR–03/09

ATtiny48/88

12. 16-bit Timer/Counter1 with PWM

12.1

Features

• True 16-bit Design (i.e., Allows 16-bit PWM)

• Two independent Output Compare Units

• Double Buffered Output Compare Registers

• One Input Capture Unit

• Input Capture Noise Canceler

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• External Event Counter

• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

12.2

Overview

Most register and bit references in this section are written in general form, where a lower case

“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit

channel. However, when using the register or bit defines in a program, the precise form must be

used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.

The 16-bit Timer/Counter unit allows accurate program execution timing (event management),

wave generation, and signal timing measurement. A simplified block diagram of the 16-bit

Timer/Counter is shown in Figure 12-1.

Figure 12-1. 16-bit Timer/Counter Block Diagram

(1)

Note:

1. Refer to Figure 1-1 on page 2,

Table 10-5 on page 64 and Table 10-11 on page 70 for

Timer/Counter1 pin placement and description.

Clock Select

Timer/Counter

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler

ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA

TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clk

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