ATtiny48 datasheet(21/266 Pages) ATMEL

21 / 266 page

8008C–AVR–03/09

ATtiny48/88

5.3.6

Preventing EEPROM Corruption

During periods of low V

CC the EEPROM data can be corrupted because the supply voltage is too

low for the CPU and the EEPROM to operate properly. These issues are the same as for board

level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by keeping the RESET active (low) during peri-

ods of insufficient power supply voltage. This can be done by enabling the internal Brown-out

Detector (BOD). If the detection level of the internal BOD does not match the needed detection

level, an external low V

CC reset Protection circuit can be used. If a reset occurs while a write

operation is in progress, the write operation will be completed provided that the power supply

voltage is sufficient.

5.4

I/O Memory

The I/O space definition of the ATtiny48/88 is shown in “Register Summary” on page 243.

All ATtiny48/88 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O Registers within the address range

0x00 – 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addresses 0x00 – 0x3F must be used. When addressing I/O Registers as data space using

LD and ST instructions, 0x20 must be added to these addresses. The ATtiny48/88 is a complex

microcontroller with more peripheral units than can be supported within the 64 location reserved

in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 – 0xFF in

SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers contain-

ing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

5.4.1

General Purpose I/O Registers

ATtiny48/88 contains three General Purpose I/O Registers. These registers can be used for

storing any information, and they are particularly useful for storing global variables and Status

Flags. General Purpose I/O Registers within the address range 0x00 – 0x1F are directly bit-

accessible using the SBI, CBI, SBIS, and SBIC instructions.

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