ATtiny48 datasheet(33/266 Pages) ATMEL

33 / 266 page

8008C–AVR–03/09

ATtiny48/88

Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during

the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.

See “Software BOD Disable” on page 34 for more details.

7.1

Sleep Modes

Figure 6-1 on page 25 presents the different clock systems in the ATtiny48/88, and their distribu-

tion. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different

sleep modes, their wake up sources and the BOD disable ability.

Notes:

1. For INT1 and INT0, only level interrupt

To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP

instruction must be executed. The SM1, and SM0 bits in the SMCR Register select which sleep

mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruction.

See Table 7-2 on page 36 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

Note that if a level triggered interrupt is used for wake-up the changed level must be held for

some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See

“External Interrupts” on page 48 for details.

7.1.1

Idle Mode

When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing the SPI, Analog Comparator, ADC, 2-wire Serial Interface,

Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode

basically halts clk

CPU and clkFLASH, while allowing the other clocks to run.

Table 7-1.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes

Sleep Mode

Active Clock Domain

Oscillator

Wake-up Source

Idle

ADC Noise Reduction

X(1)

Power-down

X(1)

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