ATtiny48 datasheet(51/266 Pages) ATMEL

51 / 266 page

8008C–AVR–03/09

ATtiny48/88

9.3.2

EIMSK – External Interrupt Mask Register

• Bits 7..2 – Res: Reserved Bits

These bits are unused in ATtiny48/88, and will always read as zero.

• Bit 1 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control bits (ISC11 and ISC10) in the External

Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising

and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt

request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt

Request 1 is executed from the INT1 Interrupt Vector.

• Bit 0 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External

Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising

and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt

request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt

Request 0 is executed from the INT0 Interrupt Vector.

9.3.3

EIFR – External Interrupt Flag Register

• Bit 7..2 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 1 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set

(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT1 is configured as a level interrupt.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

Bit

76543

210

–––––

–

INT1

INT0

EIMSK

Read/Write

RRRR

R/W

Initial Value

00000

000

Bit

76543

210

–––––

–

INTF1

INTF0

EIFR

Read/Write

RRRR

R/W

Initial Value

00000

000

ATtiny48 Datasheet(PDF) 51 Page - ATMEL Corporation

ATtiny48 Datasheet(HTML) 51 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL