ATtiny48 datasheet(52/266 Pages) ATMEL

52 / 266 page

8008C–AVR–03/09

ATtiny48/88

9.3.4

PCICR – Pin Change Interrupt Control Register

• Bit 7..4 – Res: Reserved Bits

These bits are reserved and will always read zero.

•Bit 3 – PCIE3: Pin Change Interrupt Enable 3

When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 3 is enabled. Any change on any enabled PCINT27..24 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI3

Interrupt Vector. PCINT27..24 pins are enabled individually by the PCMSK3 Register.

•Bit 2 – PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2

Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.

•Bit 1 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1

Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.

•Bit 0 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-

rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

9.3.5

PCIFR – Pin Change Interrupt Flag Register

• Bit 7..4 – Res: Reserved Bits

These bits are reserved and will always read zero.

•Bit 3 – PCIF3: Pin Change Interrupt Flag 3

When a logic change on any PCINT27..24 pin triggers an interrupt request, PCIF3 becomes set

(one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

Bit

76543

210

––––

PCIE3

PCIE2

PCIE1

PCIE0

PCICR

Read/Write

R/W

Initial Value

00000

000

Bit

76543

210

––––

PCIF3

PCIF2

PCIF1

PCIF0

PCIFR

Read/Write

R/W

Initial Value

00000

000

ATtiny48 Datasheet(PDF) 52 Page - ATMEL Corporation

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