ATtiny48 datasheet(102/266 Pages) ATMEL

102 / 266 page

102

8008C–AVR–03/09

ATtiny48/88

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

As Figure 12-9 shows the output generated is, in contrast to the phase correct mode, symmetri-

cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising

and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore

frequency correct.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,

if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as

TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-

forms on the OC1x pins. Setting the COM1x1:0 bits to 0b10 will produce a non-inverted PWM

and an inverted PWM output can be generated by setting the COM1x1:0 to 0b11 (See Table 12-

4 on page 106). The actual OC1x value will only be visible on the port pin if the data direction for

the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clear-

ing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter

increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and

TCNT1 when the counter decrements. The PWM frequency for the output when using phase

and frequency correct PWM can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be set to high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A

is used to define the TOP value and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty

cycle.

12.10 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

T1) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for

modes utilizing double buffering). Figure 12-10 shows a timing diagram for the setting of OCF1x.

OCnxPFCPWM

clk_I/O

2 NTOP

⋅⋅

----------------------------

ATtiny48 Datasheet(PDF) 102 Page - ATMEL Corporation