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ST7571 Datasheet(PDF) 63 Page - Sitronix Technology Co., Ltd. |
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ST7571 Datasheet(HTML) 63 Page - Sitronix Technology Co., Ltd. |
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63 / 76 page  ST7571 Ver 1.5a 63/76 2009/7/21 Serial I 2C Interface Fig. 35 (VDD1 = 3.3V, Ta =-30~85 °C ) Rating Item Signal Symbol Condition Min. Max. Units SCL clock frequency SCL FSCLK - 400 kHZ SCL clock low period SCL TLOW 1.3 - us SCL clock high period SCL THIGH 0.6 - us Data set-up time SDA TSU;Data 100 - ns Data hold time SDA THD;Data 0 0.9 us SCL,SDA rise time SCL TR 20+0.1Cb 300 ns SCL,SDA fall time SCL TF 20+0.1Cb 300 ns Capacitive load represented by each bus line Cb - 400 pF Setup time for a repeated START condition SDA TSU;SUA 0.6 - us Start condition hold time SDA THD;STA 0.6 - us Setup time for STOP condition TSU;STO 0.6 - us Tolerable spike width on bus TSW - 50 ns BUS free time between a STOP and START condition SCL TBUF 1.3 us Note: l All timing is specified using 20% and 80% of VDD1 as the standard. l It is recommended to operate the I 2C interface with VDD1 higher than 2.6V. |
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