ST7571 datasheet(10/76 Pages) SITRONIX

10 / 76 page

ST7571

Ver 1.5a

10/76

2009/7/21

6. PIN DESCRIPTION

6.1 POWER SUPPLY

Power Supply Pin Description

Name

I/O

Description

VDD1

Power

Power supply for digital circuit.

If VDD1 is the same level as VDD2, they can be connected together by FPC.

VDD2

Power

Power supply for analog circuit (booster).

VDD3

Power

Power supply for sensitive circuit (internal Vref regulator).

VDD3 is the same level as VDD2, and they should be connected together by FPC.

VSS1

Power

Ground for digital circuit. VSS1, VSS2 & VSS3 should be connected together by FPC.

VSS2

Power

Ground for analog circuit (booster), it should be connected together by FPC.

VSS3

Power

Ground for sensitive circuit (Vref regulator), it should be connected together by FPC.

6.2 LCD DRIVER SUPPLY

LCD Driver Supply Pin Description

Name

I/O

Description

V0O

V0I

V0S

Power

V0 is the LCD driving voltage for common circuits at negative frame.

V0O is the output of V0 regulator. V0S is the feedback of V0 regulator.

V0I is the V0 input of common circuits.

Be sure that: V0

≥ VG > VM > VSS ≥ XV0 (under operation).

V0O, V0I & V0S should be connected together by FPC.

XV0O

XV0I

XV0S

Power

XV0 is the LCD driving voltage for common circuits at positive frame.

XV0O is the output of XV0 regulator. XV0S is the feedback of XV0 regulator.

XV0I is the XV0 input of common circuits.

XV0O, XV0I & XV0S should be connected together by FPC.

VGO

VGI

VGS

Power

VG is the LCD driving voltage for segment circuits.

A storage capacitor on FPC or system for VG is required.

VGO is the output of VG regulator. VGS is the feedback of VG regulator.

VGI is the VG input of segment circuits.

VGO, VGI & VGS should be connected together by FPC.

Be aware that: 1.8V

≤ VG < VDD2.

VMO

Power

VMO is the output of VM, which is the LCD driving voltage for common circuits.

A storage capacitor on FPC or system for VM is required.

Be aware that: 0.7V < VM < VDD2.

When the internal power circuit is active, the VG and VM are generated according to the bias

setting as shown below:

LCD bias

1/N bias

(2/N) x V0

(1/N) x V0

NOTE: N = 5 to 12

ST7571 Datasheet(PDF) 10 Page - Sitronix Technology Co., Ltd.

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