ST7571 datasheet(13/76 Pages) SITRONIX

13 / 76 page

ST7571

Ver 1.5a

13/76

2009/7/21

Name

I/O

Description

When using parallel interface:

DB[7:0] are 8-bit data bus.

DB[7:0] are connected to the 8-bit data bus of a standard microprocessor.

When chip select is not active (CSB=H), DB[7:0] are high impedance.

When using 3-Line/4-Line serial interface:

DB7: serial input data (SID).

DB6: serial input clock (SCLK).

DB[5:0] are high impedance and must be fixed to

“H”.

When chip select is not active (CSB=H), DB[7:0] are high impedance.

DB[7:0]

I/O

When using I

2C interface:

DB7: SCL, serial clock input.

DB[6:4]: SDA_IN, serial input data.

DB[3:2]: SDA_OUT, output the acknowledge signal of the I

2C interface protocol.

DB[6:2] must be connected together (SDA).

DB[1:0]: SA[1:0], I

2C slave address bits of ST7571. Must connect to VDD1 or VSS1.

By connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully I

2C interface compatible. Separating

acknowledge-output from serial data input is advantageous for chip-on-glass (COG) applications. In COG

applications, the ITO resistance and the pull-up resistor will form a voltage divider, which affects acknowledge-signal

level. Larger ITO resistance will raise the acknowledged-signal level and system cannot recognize this level as a valid

logic

“0” level. By separating SDA_IN from SDA_OUT, the IC can be used in a mode that ignores the acknowledge-bit.

For applications which check acknowledge-bit, it is necessary to minimize the ITO resistance of the SDA_OUT trace

to guarantee a valid low level.

After VDD1 is turned ON, any MPU interface pins cannot be left floating.

ST7571 Datasheet(PDF) 13 Page - Sitronix Technology Co., Ltd.