MAC7200 datasheet(714/976 Pages) FREESCALE

714 / 976 page

Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

636

Freescale Semiconductor

RSRC

Receiver Source Bit. When LOOPS = 1, the RSRC bit determines the source for the receiver shift register

input.

0 Receiver input internally connected to transmitter output

1 Receiver input connected externally to transmitter

Data Format Mode Bit . MODE determines whether data characters are eight or nine bits long.

0 One start bit, eight data bits, one stop bit

1 One start bit, nine data bits, one stop bit

WAKE

Wakeup Condition Bit. WAKE determines which condition wakes up the eSCI: a logic 1 (address mark)

in the most significant bit position of a received data character or an idle condition on the RXD.

0 Idle line wakeup

1 Address mark wakeup

Note: This is not a wakeup out of a power-save mode, it refers solely to the receiver standby mode.

ILT

Idle Line Type Bit. ILT determines when the receiver starts counting logic 1s as idle character bits. The

counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a

string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the

count after the stop bit avoids false idle character recognition, but requires properly synchronized

transmissions.

0 Idle character bit count begins after start bit

1 Idle character bit count begins after stop bit

Parity Enable Bit. PE enables the parity function. When enabled, the parity function inserts a parity bit in

the most significant bit position of the transmit data. On receive data it will verify the parity bit in the most

significant bit position. The received parity bit will not be masked out, however.

0 Parity function disabled

1 Parity function enabled

Parity Type Bit. PT determines whether the eSCI generates and checks for even parity or odd parity. With

even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With

odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.

0 Even parity

1 Odd parity

Table 31-6. SCICR1 Field Descriptions (Continued)

Field

Description

LOOPS

RSRC

Function

Normal operation

Loop mode with Rx input internally connected to Tx output

Single-wire mode with Rx input connected to TXD

MAC7200 Datasheet(PDF) 714 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 714 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL