MAC7200 datasheet(715/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

637

31.9.2.3

SCI Control Register 2

Address Offset: 0x3

Access: User read/write

765

43210

TIE

TCIE

RIE

ILIE

RWU

SBK

Reset

00000000

Figure 31-5. SCI Control Register 2 (SCICR2)

Table 31-7. SCICR2 Field Descriptions

Field

Description

TIE

Transmitter Interrupt Enable Bit. TIE enables the transmit data register empty flag TDRE to generate

interrupt requests.

0 TDRE interrupt requests disabled

1 TDRE interrupt requests enabled

TCIE

Transmission Complete Interrupt Enable Bit. TCIE enables the transmission complete flag TC to generate

interrupt requests.

0 TC interrupt requests disabled

1 TC interrupt requests enabled

RIE

Receiver Full Interrupt Enable Bit. RIE enables the receive data register full flag RDRF to generate

interrupt requests.

0 RDRF interrupt requests disabled

1 RDRF interrupt requests enabled

ILIE

Idle Line Interrupt Enable Bit. ILIE enables the idle line flag IDLE to generate interrupt requests.

0 IDLE interrupt requests disabled

1 IDLE interrupt requests enabled

Transmitter Enable Bit. TE enables the eSCI transmitter and configures the TXD pin as being controlled

by the eSCI. The TE bit can be used to queue an idle preamble.

0 Transmitter disabled

1 Transmitter enabled

Receiver Enable Bit. RE enables the eSCI receiver. RE can be cleared to discard the current frame.

0 Receiver disabled

1 Receiver enabled

RWU

Receiver Wakeup Bit. Standby state.

0 Normal operation.

1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware

wakes the receiver by automatically clearing RWU (see Section 31.10.5.6, “Receiver Wakeup”).

SBK

Send Break Bit. Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics

0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished

transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or

11 bits, respectively 13 or 14 bits).

0 No break characters

1 Transmit break characters

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