MAC7200 datasheet(719/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

641

Address Offset: 0x8

Access: User read (write to clear)

765

43210

TDRE

RDRF

IDLE

Reset

00000000

Figure 31-10. SCI Status Register 1 (SCISR1)

Table 31-11. SCISR1 Field Descriptions

Field

Description

TDRE

Transmit Data Register Empty Flag. TDRE is being set when the transmit data register (SCIDRH/L)

becomes empty and can receive a new value to transmit. TDRE is 0 immediately after reset, a short time

after the module is turned on (setting MDIS=0) the eSCI will become ready, and TDRE will be set. Clear

TDRE by writing it with 1.

Transmit Complete Flag. TC is being set after a byte of data, a preamble, or a break character has been

transmitted and no data is queued via the SCI Data Register (SCIDR, Figure 31-9). When TC is set it

indicates that the TXD out signal has become idle (logic 1). Clear TC by writing it with 1.

After the device is switched on (by clearing the MDIS bit, see SCICR3 Figure 31-6) a preamble is

transmitted - if no byte is written to the the SCI Data Register then the completion of the preamble can be

monitored using the TC flag.

RDRF

Receive Data Register Full Flag. RDRF is being set when the SCI data register is loaded with new

received data. Clear RDRF by writing it with 1.

IDLE

Idle Line Flag. IDLE is being set when 10 consecutive logic 1s (if M=0) or 11 consecutive logic 1s (if M=1)

have appeared on the receiver input. Once the IDLE flag is cleared, a valid frame must again set the

RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by writing it with 1.

Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag.

Overrun Flag. OR is set when software fails to read the SCI data register before the receive shift register

receives the next frame. The OR bit is set immediately after the stop bit has been completely received for

the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not

affected. Clear OR by writing it with 1.

Noise Flag. NF is set when the eSCI detects noise on the receiver input. NF bit is set during the same

cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by writing it with 1.

Framing Error Flag. FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same

cycle as the RDRF flag but does not get set in the case of an overrun. Clear FE by writing it with 1.

Note: In LIN mode this bit will not be set when break characters are transmitted.

Parity Error Flag. PF is set when the parity enable bit PE is set and the parity of the received data does

not match its parity bit. Clear PF by writing it with 1.

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