MAC7200 datasheet(720/976 Pages) FREESCALE

720 / 976 page

Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

642

Freescale Semiconductor

31.9.2.8

SCI Status Register 2

31.9.2.9

LIN Status Register 1

Address Offset: 0x9

Access: User read/write (write to clear)

765

43210

000

BERR

000

RAF

Reset

00000000

Figure 31-11. SCI Status Register 2 (SCISR2)

Table 31-12. SCISR2 Field Descriptions

Field

Description

7–5

Reserved, should be cleared.

BERR

Bit Error. Indicates a Bit on the bus did not match the transmitted Bit. Checking happens after a complete

byte has been transmitted and received again. (A Bit Error will cause the LIN FSM to reset.) This bit is

only used for LIN mode.

If an unrequested byte is received (i.e. a byte which is not part of an RX frame) which is not recognized

as a wakeup flag then this flag is also set. (Since the data on the RX line does not match the idle state

which was assigned to the TX line.)

The flag is set when the condition is detected, cleared by a write with 1.

3–1

Reserved, should be cleared.

RAF

Receiver Active Flag. RAF is set when the receiver detects a logic 0 during the RT1 time period of the

start bit search. RAF is cleared when the receiver detects an idle character.

Writing RAF has no

effect

0 No reception in progress

1 Reception in progress

Address Offset: 0xA

Access: User read/write (write to clear)

765

43210

RXRDY

TXRDY

LWAKE

STO

PBERR

CERR

CKERR

FRC

Reset

00000000

Figure 31-12. LIN Status Register 1 (LINSTAT1)

Table 31-13. LINSTAT1 Field Descriptions

Field

Description

RXRDY

Receive Data Ready. The eSCI has received LIN data. This bit is set when the LINRX register receives a

byte. Clear RXRDY by writing it with 1.

TXRDY

Transmit Data Ready. The LIN FSM can accept another write to LINTX. This bit is set when the LINTX

(setting MDIS=0) the eSCI will become ready, and TXRDY will be set. Clear TXRDY by writing it with 1.

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