MAC7200 datasheet(724/976 Pages) FREESCALE

724 / 976 page

Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

646

Freescale Semiconductor

31.9.2.12 LIN TX Register

The first byte written to the register selects the transmit address, the second byte determines the frame

length, the third and fourth byte set various frame options and determine the timeout counter. (Header

parity will be automatically generated if the PRTY bit is set.) For TX frames the fourth byte (bits T7 - T0)

will be skipped, since the timeout function does not apply. All following bytes are data bytes for the frame.

CRC and Checksum bytes will be automatically appended when the appropriate options are selected.

When a Bit error is detected an interrupt is set, and the transmission aborted. The register can only be

written again once the interrupt is cleared. Afterwards a new frame starts, and the first byte needs to

contain a header again.

Additionally it is possible to flush the LINTX register by writing to the LRES bit.

NOTE

Not all values written to the LINTX registers will generate valid LIN frames. The values need to be

Address Offset: 0xE

Access: User read/write (with no ongoing transmissions)

765

43210

000000

UQIE

OFIE

Reset

00000000

Figure 31-16. LIN Control Register 3 (LINCTRL3)

Table 31-17. LINCTRL3 Field Descriptions

Field

Description

7–2

Reserved, should be cleared.

UQIE

Unrequested Data Interrupt Enable. Generates an Interrupt when unrequested data has been observed

on the LIN bus.

OFIE

Overflow Interrupt Enable. Generates an Interrupt when a data byte in the LINRX register hasn’t been

read before the next databyte is received.

MAC7200 Datasheet(PDF) 724 Page - Freescale Semiconductor, Inc