MAC7200 datasheet(726/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

648

Freescale Semiconductor

31.9.2.13 LIN RX Register

NOTE

The application software must ensure that LINRX is read before new Bytes

(data Bytes, CRC or checksum Bytes) are received from the LIN bus.

Similarly if data is available in LINRX, the register must be read before

starting a new frame.

Timeout Bit n. Sets the counter to determine a NO_RESPONSE_ERROR, if the frame is a read access

to a LIN slave - according to LIN standard rev 1.3 the value needs to be

Eqn. 31-2

The counter value represent the maximum time available for a complete RX frame (please refer to the LIN

specification for details). For transmissions the accessible timeout bits have to be set to 0. The timeout

bits 7-0 will not be written on a TX frame, at all. So for TX frames the 4th byte written to the TX register is

the first data byte, for RX it contains timeout bits 7-0. The time is specified in multiples of Bit times. The

timeout period starts with the transmission of the LIN break character.

Data Bit n. Data bits for transmission.

Address Offset: 0x14

Access: User read (when RXRDY is set)

765

43210

Reset

00000000

Figure 31-18. LIN RX Register (LINRX)

Table 31-19. LINRX Field Descriptions

Field

Description

7–0

Data Bit n. This register will provide received data bytes from RX frames. It is only valid when the RXRDY

flag is set, CRC and checksum information will not be available in the RX register unless they are treated

as data. It is possible to treat CRC and checksum bytes as data, by deactivating the CSUM respectively

CRC control bits in the LINTX register - however then CRC and CSUM checking has to be performed by

software.

Table 31-18. LINTX Field Descriptions (Continued)

Field

Description

10 N

DATA

⋅

() 1.4

DATA is the number of data bytes in the frame )

(

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