MAC7200 datasheet(725/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

647

determined according to the LIN specification.

Address Offset: 0x10

Access: User write (when TXRDY is set)

Byte

765

43210

First W

ID5

ID4

ID3

ID2

ID1

ID0

Second W

Third W

HDCHK

CSUM

CRC

T11

T10

Fourth W

Fifth+ W

Reset

00000000

Figure 31-17. LIN TX Register (LINTX)

Table 31-18. LINTX Field Descriptions

Field

Description

IDn

Header Bit n. The LIN address, for LIN 1.x standard frames the length bits need to be set appropriately

(see the table below), extended frames will be recognized by their specific patterns.

Note: The values 3C, 3D, 3E and 3F of the ID-field (ID0-5) indicate command and extended frames.

Parity Bit n. When enabled, the parity bits can be generated automatically (PRTY bit in register

LINCTRL1, see Figure 31-16). Otherwise they can be provided here.

Length Bit n. Defines the length of the frame - 0 to 255 data bytes - this information is needed by the LIN

state machine in order to insert the checksum or CRC pattern as required. LIN 1.x slaves will only accept

frames with 2, 4 or 8 data bytes.

HDCHK

Header Checksum Enable. Include the header fields into the mod 256 checksum of the standard frames.

CSUM

Checksum Enable. Append a checksum byte to the end of a TX frame - verify the checksum byte of a RX

frame.

CRC

CRC Enable. Append two CRC bytes to the end of a TX frame - verify the two CRC bytes of a RX frame

are correct. If both CSUM and CRC bits are set, the LIN FSM will first append the CRC bytes, then the

checksum byte, and will expect them in this order, as well. If HDCHK is set, the CRC calculation will

include header and data bytes, otherwise just the data bytes. CRC bytes are not part of the LIN standard

- they are normal data bytes and belong to a higher-level protocol.

Transmit Direction. Indicates a TX frame i.e. the eSCI will transmit data to a slave. Otherwise an RX frame

will be assumed, and the eSCI will only transmit the header, the data bytes will be received from the slave.

0RX frame

1TX frame

ID5

ID4

data bytes

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