MAC7200 datasheet(722/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

644

Freescale Semiconductor

31.9.2.11 LIN Control Registers

UREQ

Unrequested Data on LIN Bus. Unrequested activity has been detected on the LIN bus. Since the eSCI

is used as a master node, this is normally an error condition. The flag is not set if the activity is identified

as a wakeup or break character. In addition the RXRDY flag will also be set, the LINRX register must be

read before normal operations can proceed. The flag is set when the condition is detected, cleared by a

write with 1.

OVFL

RX Register Overflow. The RX register hasn’t been read before a new data byte, CRC or checksum byte

has been received from the LIN bus. The flag is set when the condition is detected, cleared by a write with

Address Offset: 0xC

Access: User read/write (with no ongoing transmissions)

765432

LRES

WUD1

WUD0

LDBG

DSF

PRTY

LIN

WWU

Reset

000000

Figure 31-14. LIN Control Register 1 (LINCTRL1)

Table 31-15. LINCTRL1 Field Descriptions

Field

Description

LRES

LIN Resync. Causes the LIN protocol engine to return to start state. This happens automatically after bit

errors, but software can force that behaviour manually via this bit. The bit needs to be first set then

cleared, so that the protocol engine is operational again. Status flags will not be affected by this bit and

will need to be cleared manually, if desired.

LIN Bus WakeUp. Generates a wakeup signal on the LIN bus. This needs to be send before a

transmission, if the bus is in sleep mode, e.g. because it has been idle for 25000 bit times. This bit will

auto-clear, so a read from this bit will always return 0. When using this feature the guidelines in

Section 31.10.11.5, “LIN Wakeup,” should be noted.

5–4

WUDn

WakeUp Delimiter Time. Determines how long the LIN engine waits after generating a wakeup signal,

before starting a new frame. The eSCI will not set TXRDY before this time expires. Note that in addition

to this delimiter time, the CPU and the eSCI will require some setup time to start a new transmission,

typically there’ll be an additional bit time delay.

LDBG

LIN Debug Mode. Prevents the LIN FSM from automatically resetting, after an exception (Bit Error,

Physical Bus Error, Wakeup Flag) has been detected. This is for debug purposes only.

Table 31-14. LINSTAT2 Field Descriptions (Continued)

Field

Description

WUD1

WUD0

bit times

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