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MAC7200 Datasheet(PDF) 723 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 723 Page - Freescale Semiconductor, Inc

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Memory Map and Register Definition
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
645
2
DSF
Double Stop Flags. When a bit error has been detected, this will add an additional stop flag to the byte in
which the error occurred.
1
PRTY
Activating Parity Generation. Generate the two Parity Bits in the LIN header.
0
LIN
LIN Mode. Switch device into LIN mode.
Note: In LIN mode data transfer should be done only via the LIN interface. The SBK bit (in SCICR2) and
the SCI data registers (SCIDRH/L) should not be used. Similarly all data transfer handshaking
should be done via the LIN interface, the TDRE, TC and RDRF flags in the SCISR1 should not be
used for that purpose.
Address Offset: 0xD
Access: User read/write (with no ongoing transmissions)
765
43210
R
RXIE
TXIE
WUIE
STIE
PBIE
CIE
CKIE
FCIE
W
Reset
00000000
Figure 31-15. LIN Control Register 2 (LINCTRL2)
Table 31-16. LINCTRL2 Field Descriptions
Field
Description
7
RXIE
LIN RXREG Ready Interrupt Enable. Generates an Interrupt when new data is available in the LIN
RXREG.
6
TXIE
LIN TXREG Ready Interrupt Enable. Generates an Interrupt when new data can be written to the LIN
TXREG.
5
WUIE
RX WakeUP Interrupt Enable. Generates an Interrupt when a wakeup flag from a LIN 1.x slave has been
received. When using this feature the guidelines in Section 31.10.11.5, “LIN Wakeup,” should be followed.
4
STIE
Slave Timeout Error Interrupt Enable. Generates an Interrupt when the slave response is too slow.
3
PBIE
Physical Bus Error Interrupt Enable. Generates an Interrupt when no valid message can be generated on
the bus.
2
CIE
CRC Error Interrupt Enable. Generates an Interrupt when a CRC error on a received extended frame is
detected.
1
CKIE
Checksum Error Interrupt Enable. Generates an Interrupt on a detected Checksum Error.
0
FCIE
Frame Complete Interrupt Enable. Generates an Interrupt after complete transmission of a TX frame, or
after the last byte of an RX frame is received. (The complete frame includes all header, data, CRC and
checksum bytes as applicable.)
Table 31-15. LINCTRL1 Field Descriptions (Continued)
Field
Description



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