MAC7200 datasheet(721/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

643

31.9.2.10 LIN Status Register 2

LWAKE

Received LIN 1.x Wakeup Signal. A LIN slave has sent a LIN 1.x wakeup signal (80h, 00h or C0h) on the

bus. When this signal is detected, the LIN FSM will reset. If the setup of a frame had already started, the

setup therefore needs to be repeated. When using this feature the guidelines in Section 31.10.11.5, “LIN

Wakeup,” should be noted.

This flag will also be set if the ESCI receives a LIN 2.0 Wakeup Signal under the conditions described in

Section 31.10.11.5, “LIN Wakeup.”

The flag is set when the condition is detected, cleared by a write with 1.

STO

Slave TimeOut. Represents a NO_RESPONSE_ERROR - this is set if a slave doesn’t complete a frame

within the specified maximum frame length. For LIN 1.3 the formula

Eqn. 31-1

is used (NDATA = number of data bytes in a frame, please refer to the LIN specification for details).

The flag is set when the condition is detected, cleared by a write with 1.

PBERR

Physical Bus Error. No valid message can be generated on the bus. This is set if after the start of a byte

transmission the input remains unchanged for 31 cycles. If the line toggles at least once during the

transmission, the bit will not be set. A PBERR condition will reset the LIN FSM. The flag is set when the

condition is detected, cleared by a write with 1.

CERR

CRC Error. The CRC pattern received with an extended frame was not correct. The flag is set when the

condition is detected, cleared by a write with 1.

CKERR

Checksum Error. Checksum Error on a received frame. The flag is set when the condition is detected,

cleared by a write with 1.

FRC

Frame Complete. LIN frame completely transmitted / All LIN data bytes (including checksum/CRC if

applicable) received. The flag is set when the condition is detected, cleared by a write with 1.

Address Offset: 0x8

Access: User read/write (write to clear)

765

43210

000000

UREQ

OVFL

Reset

00000000

Figure 31-13. LIN Status Register 2 (LINSTAT2)

Table 31-14. LINSTAT2 Field Descriptions

Field

Description

7–2

Reserved, should be cleared.

Table 31-13. LINSTAT1 Field Descriptions (Continued)

Field

Description

FRAME MAX

10 N

DATA

⋅

() 1.4

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