MAC7200 datasheet(717/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

639

31.9.2.5

SCI Control Register 4

31.9.2.6

SCI Data Registers

Reading this register accesses eSCI receive data register. Writing accesses eSCI transmit data register;

writing to R8 has no effect; register is not writable in LIN mode

Address Offset: 0x5

Access: User read/write

765

43210

BESM13

SBSTP

PMSK

ORIE

NFIE

FEIE

PFIE

Reset

00000000

Figure 31-7. SCI Control Register 4 (SCICR4)

Table 31-9. SCICR4 Field Descriptions

Field

Description

BESM13

Bit Error Sample Mode, Bit 13. Determines when to sample the incoming bit in order to detect a bit error.

(This is only relevant in LIN mode and when FBR is set.)

0 Sample at RT clock 9

1 Sample at RT clock 13 (see Section 31.10.5.3, “Data Sampling”)

SBSTP

SCI Bit Error Stop. Stops the SCI when a Bit Error is asserted. This allows to stop driving the LIN bus

quickly after a Bit Error has been detected. The SCI won’t start a new byte transmission until the time for

the current byte has expired. This bit is only relevant in LIN mode.

Reserved, should be cleared.

PMSK

Parity Mask. Forces bit 7 in the Data Register to 0 on reads. This can be used to mask the parity bit in

application which use 7 data bits and 1 parity bit.

ORIE

Overrun Error Interrupt Enable. Generates an interrupt, when Overrun flag is set.

NFIE

Noise Flag Interrupt Enable. Generates an interrupt, when Noise Flag is set.

FEIE

Frame Error Interrupt Enable. Generates an interrupt, when a Frame Error is detected.

PFIE

Parity Flag Interrupt Enable. Generates an interrupt, when Parity Flag is set.

Address Offset: 0x6

Access: User read/write

765

43210

RR8

000000

Reset

00000000

Figure 31-8. SCI Data Register High (SCIDRH)

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