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MAC7200 Datasheet(PDF) 786 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 786 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
708
Freescale Semiconductor
Figure 32-24. Pulse/Edge Accumulation single-shot mode example
32.13.1.1.8
Pulse/Edge Counting (PEC) Mode
The PEC mode returns the amount of pulses or edges detected on the input for a desired time window.
MODE[0] bit selects between continuos or single shot operation.
Triggering of the internal counter is done by a rising or falling edge or both edges on the input signal. The
polarity and the triggering edge is selected by EDSEL and EDPOL bits in UCCRn register.
Register A1 holds the start time and register B1 holds the stop time for the time window. After writing to
register A1, when a match occur between comparator A and the selected timebase, the internal counter is
cleared and it is ready to start counting input events. When the time base matches comparator B, the
internal counter is disabled and its content is transferred to register A2. At the same time the FLAG bit is
set. Reading registers MSTCNTn or A2 returns the amount of detected pulses.
For continuos operation (MODE[0] cleared), the next match between comparator A and the selected time
base clears the internal counter and counting is enabled again. In order to guarantee coherent
measurements when reading UCCNTn after the flag is set, the software must check if the time base value
is out of the time interval defined by registers A1 and B1. Alternatively register A2 always holds the latest
available measurement providing coherent data at any time after the first FLAG had occurred. This register
is addressed by the alternate address ALTAn.
For single shot operation (MODE[0] set), the next match between comparator A and the selected time base
has no effect, until a new write to register A is performed. The UCCNTn content is also transferred to
register A2 when a match in the B comparator occurs.
$FFFFFF
$000000
UCCNTn1
Time
write to A1
selected counter bus
$000400
A1 value3
$001500
$xxxxxx
A2
value4
$000400
$xxxxxx
B1
value
$000090
$xxxxxx
B2
value5
$xxxxxx
$001500
$000090
$000090
FLAG set event
$001500
input signal2
A1 events
Notes:
4. UCAn = A2 (when reading)
5. UCBn = B1
3. UCAn = A1 (when writing)
2. After input filter
events
events
$000400
1. Cleared on the first input event after writing to register A1
A1 Match
MODE[0]= 1



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