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MAC7200 Datasheet(PDF) 785 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 785 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
707
In order to guarantee coherent access, reading UCAn disables transfers between B2 and B1. These
transfers are disabled until the next read of the UCBn register. Reading the UCBn register re-enables
transfers from B2 to B1, to take effect at the next transfer event, as described above.1
Triggering of the counter clock (input event) is done by a rising or falling edge or both edges on the input
pin. The polarity of the triggering edge is selected by the EDSEL and EDPOL bits in UCCRn register.
For continuos operation mode (MODE[0] cleared), the counter is cleared on the next input event after a
FLAG generation and continues to operate as described above.
For single shot operation (MODE[0] set), the counter is not cleared or incremented after a FLAG
generation, until a new writing operation to register A is performed.
Figure 32-23 and Figure 32-24 show how the Unified Channel can be used for continuos and single shot
pulse/edge accumulation mode.
Figure 32-23. Pulse/Edge Accumulation continuous mode example
1. If B1 was not updated due to B2 to B1 transfer being disabled after reading register UCAn, further UCAn and UCBn reads will
not return coherent data until a new bus capture is triggered to registers A2 and B2. This capture event is indicated by the
channel FLAG being asserted. If enabled, the FLAG also generates an interrupt.
$FFFFFF
$000000
UCCNTn1
Time
A1 Match
write to A1
selected counter bus
$000400
A1 value3
$001500
$xxxxxx
A2
value4
$000400
$xxxxxx
B1
value
$000090
$xxxxxx
B2
value5
$001000
$xxxxxx
$001500
$000090
$000090
$007000
$001500
$007000
$001000
FLAG set event
A1 Match
$001500
input signal2
$001000
A1 events
A1 events
no events
events
$000400
Notes:
4. UCAn = A2 (when reading)
5. UCBn = B1
3. UCAn = A1 (when writing)
2. After input filter
1. Cleared on the first input event after writing to register A1
$007000
MODE[0]= 0



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