MAC7200 datasheet(781/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

703

In order to guarantee coherent access, reading UCAn forces B1 be updated with the content of register A1.

At the same time transfers between B2 and B1 are disabled until the next read of UCBn register. Reading

UCBn register forces B1 be updated with A1 register content and re-enables transfers from B2 to B1, to

take effect at the next trailing edge capture. Transfers from B2 to A1 are not blocked at any time.

The input pulse width is calculated by subtracting the value in B1 from A2.

Figure 32-17 shows how the Unified Channel can be used for input pulse width measurement.

Figure 32-17. Input Pulse Width Measurement example

Figure 32-18 shows the A1 and B1 updates when UCAn and UCBn register reads occur. Note that A1

coherent data related to the last UCAn read. The B1 register updates remains locked until UCBn read

occurs. If UCAn read is performed B1 is updated with A1 register content even if B1 update is locked by

a previous UCAn read operation.

Figure 32-18. B1 and A1 updates at UCAn and UCBn reads

selected counter bus

$000500

$001000

$001100

$001250

$001525

$0016A0

A2(captured) value2

B2(captured) value

B1 value3

$xxxxxx

$001000

$001250

$0016A0

$xxxxxx

$001100

$001525

$xxxxxx

$001000

$001250

Input signal1

BAB

1. After input filter

Notes:

FLAG set event

2. UCAn = A2

3. UCBn = B1

EDPOL = 1

A1 value3

$xxxxxx

$001000

$001250

selected counter bus

$000500

$001000

$001100

$001250

$001525

$0016A0

A2(captured) value2

B2(captured) value

B1 value3

$xxxxxx

$001000

$001250

$0016A0

$xxxxxx

$001100

$001525

$xxxxxx

$001000

Input signal1

BAB

1. After input filter

Notes:

FLAG set event

2. UCAn = A2

EDPOL = 1

A1 value3

$xxxxxx

$001000

$001250

$001000

$001250

Read UCAn

Read UCBn

3. UCBn = B1

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