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MAC7200 Datasheet(PDF) 782 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 782 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
704
Freescale Semiconductor
Reading UCAn followed by UCBn always provide coherent data. If not coherent data is required for any
reason, the sequence of reads should be inverted, therefore UCBn should be read prior to UCAn register.
Note that even in this case B1 register updates will be blocked after UCAn read, thus a second UCBn is
required in order to release B1 register updates.
32.13.1.1.5
Input Period Measurement (IPM) Mode
The IPM mode allows the measurement of the period of an input signal by capturing two consecutive rising
edges or two consecutive falling edges. Successive input captures are done on consecutive edges of the
same polarity. The edge polarity is defined by the EDPOL bit in the UCCRn register.
When the first edge of selected polarity is detected, the selected time base is latched into the registers A2
and B2, and the data previously held in register B2 is transferred to register B1. On this first capture the
FLAG line is not set, and the values in registers B1 is meaningless. On the second and subsequent captures,
the FLAG line is set and data in register B2 is transferred to register B1.
When the second edge of the same polarity is detected, the counter bus value is latched into registers A2
and B2, the data previously held in register B2 is transferred to data register B1 and to register A1. The
FLAG bit is set to indicate the start and end points of a complete period have been captured. This sequence
of events is repeated for each subsequent capture. Registers UCAn and UCBn return the values in register
A2 and B1, respectively.
In order to allow coherent data, reading UCAn forces A1 content be transferred to B1 register and disables
transfers between B2 and B1. These transfers are disabled until the next read of the UCBn register.
Reading UCBn register forces A1 content to be transferred to B1 and re-enables transfers from B2 to B1,
to take effect at the next edge capture.
The input pulse period is calculated by subtracting the value in B1 from A2.
Figure 32-19 shows how the Unified Channel can be used for input period measurement.
Figure 32-19. Input Period Measurement example
Figure 32-20 describes the A1 and B1 register updates when UCAn and UCBn read operations are
performed. When UCAn read occurs the content of A1 is transferred to B1 thus providing coherent data
selected counter bus
$000500
$001000
$001100
$001250
$001525
$0016A0
A2(captured) value2
A1 value
B2 (captured) value
$xxxxxx
$xxxxxx
$001000
$001250
$xxxxxx
$001000
$001250
$0016A0
$xxxxxx
$001000
$001250
$0016A0
Input signal1
EDPOL = 1
FLAG set event
Notes: 1. After input filter
2. UCAn = A2
3. UCBn = B1
A
A
A
B1 value3
$xxxxxx
$xxxxxx
$001000
$001250



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