MAC7200 datasheet(778/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

700

Freescale Semiconductor

Figure 32-13. Unified Channel Block Diagram

32.13.1.1 UC Modes of Operation

The mode of operation of the Unified Channel is determined by the mode select bits MODE[6:0] in the

UCCRn register (see Table 32-16 for details).

When entering an output mode (except for GPIO mode), the output flip-flop is set to the complement of

the EDPOL bit in the UCCRn register.

As the internal counter UCCNTn continues to run in all modes (except for GPIO mode), it is possible to

use this as a time base if the resource is not used in the current mode.

In order to provide smooth waveform generation even if A and B registers are changed on the fly, it is

available the MCB, OPWFMB, OPWMB and OPWMCB modes. In these modes A and B registers are

double buffered. They are presented in separated sections since there are several basic differences between

these and the MC, OPWFM, OPWM and OPWMC modes, respectively.

Notes:

comparator A

Counter Bus

RWCB

select

FLAG

internal counter

comparator B

EMIOSOn

output flip-flop

Prgm.

filter

To register B

Edge

detect

To register A

EMIOSIn

counter bus [A]

counter bus [B]

EDPOL EDSEL

FSM

RQB

IIB

prescaler

see note 1

UCPRE

BSL

MODE

FORCMB

FORCMA

FCK IF

UCIN

UCOUT

ipp_obe_mts_ucn

Unified Channel

internal counter clock

UCPREN

To internal counter

UPDATE

ODIS

ODISSL

Output disable control Bus

see note 2

2. Goes to the FSM of the UC[n-1]. These signals

1. See Figure 32-1 to check how the counter buses

are used for QDEC mode.

[6:0]

[1:0]

[3:0]

(with zero detection)

mts_flag_outn

driven.

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