MAC7200 datasheet(776/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

698

Freescale Semiconductor

32.12.2.10 eMIOS Alternate A Register (ALTAn)

The ALTAn register provides an alternate read only address to access A2 channel registers in PEC and

WPTA modes only. If UCAn register is used along with ALTAn, both A1 and A2 registers can be accessed

in these modes. Please, see Section 32.13.1.1.8, “Pulse/Edge Counting (PEC) Mode and

Section 32.13.1.1.10, “Windowed Programmable Time Accumulation (WPTA) Mode” for a more detailed

description of the use of ALTAn register.

OVFL

OVRC

OVFL — Overflow bit

The OVFL bit indicates that an overflow has occurred in the internal counter. OVFL must be cleared by software

writing a 1 to the OVFLC bit.

0 No overflow

1 An overflow had occurred

OVFLC — Overflow Clear bit

The OVFL bit must be cleared by writing a 1 to the OVFLC.

0 Do not change OVFL bit

1 Clear OVFL bit

14–3

Reserved, should be cleared

UCIN

Unified Channel Input pin bit

The UCIN bit reflects the input pin state after being filtered and synchronized.

UCOUT

Unified Channel Output pin bit

The UCOUT bit reflects the output pin state.

FLAG

FLAGC

FLAG — FLAG bit

The FLAG bit is set when an input capture or a match event in the comparators occurred.

0 FLAG cleared

1 FLAG set event has occurred

Note: mts_flag_out reflects the FLAG bit value. When DMA bit is set, the FLAG bit can be cleared by the DMA

controller.

FLAGC — FLAG Clear bit

The FLAG bit must be cleared by writing a 1 to FLAGC.

0 Do not change FLAG bit

1 Clear FLAG bit

Table 32-17. UCSRn Field Descriptions (Continued)

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