MAC7200 datasheet(773/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

695

10–9

BSL[1:0]

Bus Select bitsThe BSL[1:0] bits are used to select either one of the counter buses or the internal counter to be

used by the Unified Channel. Refer toTable 32-15 for details.

EDSEL

Edge Selection bit.

For input modes, the EDSEL bit selects whether the internal counter is triggered by both edges of a pulse or just

by a single edge as defined by the EDPOL bit. When not shown in the mode of operation description, this bit has

no effect.

0 Single edge triggering defined by the EDPOL bit

1 Both edges triggering

For GPIO in mode, the EDSEL bit selects if a FLAG can be generated.

0 A FLAG is generated as defined by the EDPOL bit

1 No FLAG is generated

For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match.

0 The EDPOL value is transferred to the output flip-flop

1 The output flip-flop is toggled

EDPOL

Edge Polarity bit.

For input modes (except QDEC mode), the EDPOL bit asserts which edge triggers either the internal counter or

an input capture or a FLAG. When not shown in the mode of operation description, this bit has no effect.

0 Trigger on a falling edge

1 Trigger on a rising edge

For QDEC (MODE[0] cleared), the EDPOL bit selects the count direction according to direction signal (UCn input).

0 counts down when UCn is asserted

1 counts up when UCn is asserted

Note: UC[n-1] EDPOL bit selects which edge clocks the internal counter of UCn

0 Trigger on a falling edge

1 Trigger on a rising edge

For QDEC (MODE[0] set), the EDPOL bit selects the count direction according to the phase difference.

0 internal counter decrements if phase_A is ahead phase_B signal

1 internal counter increments if phase_A is ahead phase_B signal

Note: In order to operate properly, EDPOL bit must contain the same value in UCn and UC[n-1]

For output modes, the EDPOL bit is used to select the logic level on the output pin.

0 A match on comparator A clears the output flip-flop, while a match on comparator B sets it

1 A match on comparator A sets the output flip-flop, while a match on comparator B clears it

6–0

MODE[6:0]

The MODE[6:0] bits select the mode of operation of the Unified Channel, as shown in Table 32-16.

Table 32-11. UCCRn Field Descriptions (Continued)

Table 32-15. BSL Bits

BSL[1:0]

selected bus

All channels: counter bus[A]

Channels 0 to 7: counter bus[B]

reserved

All channels: internal counter

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