MAC7200 datasheet(770/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

692

Freescale Semiconductor

32.12.2.8 eMIOS Control Register (UCCRn)

The Control register gathers bits reflecting the status of the UC input/output signals and the overflow

condition of the internal counter, as well as several read/write control bits.

Address UCn base address + 0x0C

FREN ODIS

DMA

IF[3:0]

FCK

FEN

Reset:

000000000000000

9876543210

00000

BSL[1:0]

MODE[6:0]

Reset:

000000000000000

= Unimplemented or reserved

Figure 32-10. eMIOS Control Register (UCCRn)

Table 32-11. UCCRn Field Descriptions

Field

Descriptions

FREN

Freeze Enable bit. The FREN bit, if set and validated by FRZ bit in MCR register, freezes all registers values when

in debug mode, allowing the MCU to perform debug functions.

0 Normal operation

1 Freeze UC registers values

ODIS

Output Disable bit. The ODIS bit allows disabling the output pin when running any of the output modes with the

exception of GPIO mode.

1 If the selected Output Disable Input signal is asserted, the output pin goes to EDPOL for OPWFMB and OPWMB

modes and to the complement of EDPOL for other modes, but the Unified Channel continues to operate

normally, i.e., it continues to produce FLAG and matches. When the selected Output Disable Input signal is

negated, the output pin operates normally

0 The output pin operates normally

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