| Electronic Components Datasheet Search |
|
MAC7200 Datasheet(PDF) 768 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MAC7200 Datasheet(HTML) 768 Page - Freescale Semiconductor, Inc |
|
768 / 976 page ![]() Memory Map/Register Definition MAC7200 Microcontroller Family Reference Manual, Rev. 2 690 Freescale Semiconductor 32.12.2.6 eMIOS B Register (UCBn) Depending on the mode of operation, internal registers B1 or B2 can be assigned to address UCBn. Both B1 and B2 are cleared by reset. Table 32-10 summarizes the UCBn writing and reading accesses for all operation modes. For more information see section Section 32.13.1.1, “UC Modes of Operation”. Address UCn base address + 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 000000000000000 0 W Reset: 000000000000000 0 15 14 13 12 11 10 9876543210 R A[15:0] W Reset: 000000000000000 0 = Unimplemented or Reserved Figure 32-7. eMIOS A Register (UCAn) Address UCn base address + 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 000000000000000 0 W Reset: 000000000000000 0 15 14 13 12 11 10 9876543210 R B[15:0] W Reset: 000000000000000 0 = Unimplemented or Reserved Figure 32-8. eMIOS B register (UCBn) Table 32-10. UCAn, UCBn and ALTAn values assignment Operation Mode Register access write read write read alt read GPIO A1, A2 A1 B1,B2 B1 - SAIC1 - A2B2B2 - |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |