MAC7200 datasheet(772/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

694

Freescale Semiconductor

22–19

IF[3:0]

Input Filter bitsThe IF[3:0] bits control the programmable input filter, selecting the minimum input pulse width that

can pass through the filter, as shown in the forlowing table. . For output modes, these bits have no meaning.

FCK

Filter Clock select bit . The FCK bit selects the clock source for the programmable input filter.

0 prescaled clock

1 main clock

FEN

FLAG Enable bit. The FEN bit allows the Unified Channel FLAG bit to generate an interrupt signal or a DMA request

signal (The type of signal to be generated is defined by the DMA bit).

0 Disable (FLAG does not generate an interrupt or DMA request)

1 Enable (FlAG will generate an interrupt or DMA request)

16–14

Reserved, should be cleared.

FORCMA

Force Match A bitFor output modes, the FORCMA bit is equivalent to a successful comparison on comparator A

(except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit is valid for every

output operation mode which uses comparator A, otherwise it has no effect.

0 Has no effect

1 Force a match at comparator A

For input modes, the FORCMA bit is not used and writing to it has no effect.

FORCMB

Force Match B bit. For output modes, the FORCMB bit is equivalent to a successful comparison on comparator B

(except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit is valid for every

output operation mode which uses comparator B, otherwise it has no effect.

0 Has not effect

1 Force a match at comparator B

For input modes, the FORCMB bit is not used and writing to it has no effect.

Reserved, should be cleared.

Table 32-11. UCCRn Field Descriptions (Continued)

Table 32-14. Input Filter Bits

IF[3:0]1

1. Filter latency is 3 clock edges.

Minimum input Pulse width [FLT_CLK periods]

0000

bypassed2

2. The input signal is synchronized before arriving to the digital filter.

0001

0010

0100

1000

all others

reserved

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