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MAC7200 Datasheet(PDF) 777 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 777 Page - Freescale Semiconductor, Inc

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Functional Description
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
699
32.13 Functional Description
The eMIOS provides independent channels (UC) that can be configured and accessed by a host MCU. On
the MAC72xx, two time bases can be shared by the channels through two counter buses and each Unified
Channel can generate its own time base.
The eMIOS block is reset at positive edge of the clock (synchronous reset). All registers are cleared on
reset.
32.13.1 Unified Channel (UC)
Figure 32-13 shows the Unified Channel block diagram. Each Unified Channel consists of:
•
Counter bus selector, which selects the time base to be used by the channel for all timing functions
•
A programmable clock prescaler
•
Two double buffered data registers A and B that allow up to two input capture and/or output
compare events to occur before software intervention is needed.
•
Two comparators (equal only) A and B, which compares the selected counter bus with the value in
the data registers
•
Internal counter, which can be used as a local time base or to count input events
•
Programmable input filter, which ensures that only valid pin transitions are received by channel
•
Programmable input edge detector, which detects the rising, falling or either edges
•
An output flip-flop, which holds the logic level to be applied to the output pin
•
eMIOS Status and Control register
•
An Output Disable Input selector, which selects the Output Disable Input signal that will be used
as output disable
•
Control state machine (FSM)
Address UCn base address + 0x14
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
000
00
000
000
000
0
W
Reset:
0
000
00
000
000
000
0
15
14
13
12
11
10
9
876
543
210
R
ALTA[15:0]
W
Reset:
0
000
00
000
000
000
0
= Unimplemented or Reserved
Figure 32-12. eMIOS Alternate A register (ALTAn)



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